Title :
Programmable parallel coprocessor architectures for reconfigurable system-on-chip
Author :
Williams, John ; Bergmann, Neil
Author_Institution :
Sch. of ITEE, Queensland Univ., Brisbane, Qld., Australia
Abstract :
We propose a hybrid rSoC parallel processing architecture consisting of a central 32-bit RISC microprocessor interconnected to an array of 8-bit microcontrollers as coprocessing nodes. The central processor runs an embedded Linux operating system, with the coprocessor nodes mapped into a virtual file system, by which they can be controlled and reprogrammed. The hardware and software architectures are detailed, and several useful application contexts are proposed. Supporting theoretical analysis is also presented.
Keywords :
Linux; coprocessors; embedded systems; integrated circuit design; microcontrollers; parallel architectures; reconfigurable architectures; reduced instruction set computing; system-on-chip; 32 bits; 8 bits; RISC microprocessor; coprocessing nodes; embedded Linux operating system; hardware architectures; hybrid rSoC parallel processing architecture; microcontrollers; programmable parallel coprocessor architectures; reconfigurable system-on-chip; software architectures; virtual file system; Computer architecture; Coprocessors; File systems; Linux; Microcontrollers; Microprocessors; Operating systems; Parallel processing; Reduced instruction set computing; System-on-a-chip;
Conference_Titel :
Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
Print_ISBN :
0-7803-8651-5
DOI :
10.1109/FPT.2004.1393268
