DocumentCode
2549591
Title
A new low power full adder cell in CMOS inverter
Author
Zandkarimi, G. ; Navi, K. ; Mokari, H.
Author_Institution
Dept. of Electr. Eng., Islamic Azad Univ. (IAU), Tehran, Iran
fYear
2010
fDate
15-17 June 2010
Firstpage
1
Lastpage
5
Abstract
In this paper we present a novel 1-bit full adder cell. The cell offer less power consumption in comparison with the conventional and current implementation of the full adder cell, especially at low voltages. All transitions are used for simulation to obtain the delay and the power consumption parameters. Simulation is improved in term of power consumption. The new full adder cell is simulated at 0.18_μm CMOS technology, using HSPICE.
Keywords
CMOS digital integrated circuits; adders; logic gates; low-power electronics; CMOS inverter; HSPICE; less power consumption; low power full adder cell; size 0.18 mum; Adders; CMOS integrated circuits; Capacitors; Delay; Inverters; Logic gates; Power demand;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent and Advanced Systems (ICIAS), 2010 International Conference on
Conference_Location
Kuala Lumpur, Malaysia
Print_ISBN
978-1-4244-6623-8
Type
conf
DOI
10.1109/ICIAS.2010.5716112
Filename
5716112
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