PLL-less clock multiplier with self-adjusting phase symmetry

We describe a very simple clock multiplier circuit, capable of multiplying the clock frequency by an integer M and producing an output with a relatively symmetric, self-adjusting phase. The circuit is not PLL- nor DLL-based, and feedback loops are not utilized. However, contrary to PLL or DLL systems, it is intended only for relatively low frequencies generation. Experimental results from a MOSIS chip are included