A digitally calibrated R-2R ladder architecture for high performance digital-to-analog converters

The paper presents a model for R-2R ladder-based digital-to-analog converters, developed in terms of resistors´ tolerance. The widely used R-2R ladders are easy to be realized as an integrated circuit, while their performance is basically limited due to the resistors´ mismatch. However, it is possible to achieve higher linearity, in terms of integral and differential non-linearity errors, if calibration is employed. In this paper, the conventional R-2R ladder architecture is briefly discussed, and then a new digitally calibrated architecture is presented with its calibration algorithm, based on the resistors´ tolerance formulation. It has been proven by simulations that the performance of an R-2R-based digital-to-analog converter can be optimized regardless of the resistors´ tolerance and the required resolution