MIMO detection in analog VLSI

Author

Soler-Garrido, Josep ; Piechocki, Robert J. ; Maharatna, Koushik ; McNamara, Darren

Author_Institution

Centre for Commun. Res., Bristol Univ.

fYear

2006

fDate

21-24 May 2006

Abstract

In this paper we propose an analog VLSI approach to maximum a posteriori (MAP) detection in multiple-input multiple-output (MIMO) systems. This detector can be seen as an extension of the well known analog decoding concept for error correcting codes, as it is constructed using similar building blocks. Therefore, it can naturally interact with analog decoders in order to perform turbo detection in MIMO systems. First transistor-level simulations for a small analog MIMO detector in a 0.25mum BiCMOS process agree well with floating-point digital simulations

Keywords

BiCMOS analogue integrated circuits; MIMO systems; VLSI; error correction codes; floating point arithmetic; maximum likelihood detection; turbo codes; 0.25 micron; BiCMOS process; MAP detection; MIMO detection; MIMO systems; analog MIMO detector; analog VLSI; analog decoding; error correcting codes; floating-point digital simulations; maximum a posteriori detection; multiple-input multiple-output systems; transistor-level simulations; turbo detection; Analog computers; Circuits; Decoding; Detectors; Error correction codes; MIMO; Receiving antennas; Signal processing; Transmitting antennas; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693728

Filename

1693728