Bit stream processing for /spl Delta/-/spl Sigma/ FM-to-digital converters

This paper presents the novel concept of adopting bit stream processing at the output stage of a parallel Delta-Sigma FM-to-digital converter. Addition of bit streams by interleaving allows speed to be traded with circuit complexity, chip area and power consumption. The conventional implementation employing a summing tree is substituted by a simple and compact multiplexing tree. The inherent simplicity renders the converter easy to reconfigure. System theory and simulation results are presented