Decoders for low-density parity-check convolutional codes with large memory

Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and decode arbitrary lengths of data. This makes these codes well suited to certain applications, such as forward error control on packet switching networks. In this paper we propose a decoder architecture for low-density parity-check convolutional codes with very large memories. These codes have very good error correcting properties and as such may be applicable in wireless sensor networks and space communication systems. We discuss a realization of this architecture for a (2048,3,6) code implemented on a field-programmable gate-array