Towards an optimised VLSI design algorithm for the constant matrix multiplication problem

Author

Kinane, Andrew ; Muresan, Valentin ; O´Connor, Noel

Author_Institution

Centre for Digital Video Process., Dublin City Univ.

fYear

2006

fDate

21-24 May 2006

Abstract

The efficient design of multiplierless implementations of constant matrix multipliers is challenged by the huge solution search spaces even for small scale problems. Previous approaches tend to use hill-climbing algorithms risking sub-optimal results. The proposed algorithm avoids this by exploring parallel solutions. The computational complexity is tackled by modelling the problem in a format amenable to genetic programming and hardware acceleration. Results show an improvement on state of the art algorithms with future potential for even greater savings

Keywords

VLSI; computational complexity; genetic algorithms; integrated circuit design; integrated logic circuits; matrix multiplication; multiplying circuits; VLSI design; computational complexity; constant matrix multiplication problem; constant matrix multipliers; genetic programming; hardware acceleration; hill-climbing algorithms; parallel solutions; Adders; Algorithm design and analysis; Coordinate measuring machines; Design optimization; Discrete Fourier transforms; Discrete cosine transforms; Equations; Matrices; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693782

Filename

1693782