Title :
A CMOS implementation of time-interleaved high-pass /spl Delta//spl Sigma/ modulator
Author :
Nguyen, Van Tam ; Loumeau, Patrick ; Naviner, Jean-Francois
Author_Institution :
Departement Commun. et electronique, GET/Telecom Paris
Abstract :
This paper describes a successful switched-capacitor implementation in CMOS process of a time-interleaved high-pass DeltaSigma modulator that is completely immune to channel offset. As a result, a simple LMS algorithm can be used to equalize the channel gain mismatch. In this parallel architecture, second-order HP DeltaSigma modulators achieving a 59dB dynamic range with a 32 times oversampling ratio at 10 MHz sampling frequency, were used. These modulators were implemented in a 0.35mum 3.3V CMOS process. The parallel system gives almost the same performance with the oversampling ratio reduced by half
Keywords :
CMOS integrated circuits; delta-sigma modulation; high-pass filters; parallel architectures; switched capacitor filters; 0.35 micron; 10 MHz; 3.3 V; CMOS process; channel gain mismatch; channel offset; high-pass DeltaSigma modulator; least mean squares algorithm; parallel architecture; switched-capacitor networks; 1f noise; Bandwidth; CMOS process; Clocks; Filters; Least squares approximation; Low-frequency noise; Noise reduction; Noise shaping; Signal to noise ratio;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693851
