DocumentCode
2556565
Title
A delay generation technique for fast-locking frequency synthesizers
Author
Aniruddhan, Sankaran ; Shekhar, Sudip ; Allstot, David J.
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA
fYear
2006
fDate
21-24 May 2006
Lastpage
5466
Abstract
A delay generation technique applied to loop-bandwidth enhancement of frequency synthesizers is proposed for faster switching. PMOS transistors are used to provide large resistances and a diode-connected PMOS device generates the switch gate-bias voltage to reduce delay variations over process. An integer-N PLL employing the above technique for bandwidth enhancement is designed and simulated at 2.4GHz. It has a phase noise of -123dBc/Hz @ 1MHz offset. The lock time is 40mus, and the tuning range is 200MHz
Keywords
MOSFET; frequency synthesizers; phase locked loops; phase noise; PMOS transistors; bandwidth enhancement; fast-locking frequency synthesizers; lock time; phase noise; Bandwidth; Delay; Diodes; Frequency synthesizers; MOS devices; MOSFETs; Phase locked loops; Phase noise; Switches; Voltage; Frequency synthesizer; bandwidth enhancement; lock time;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693870
Filename
1693870
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