Title :
Electrostatic discharge (ESD) technology benchmarking strategy for evaluating ESD robustness of CMOS technologies
Author :
Voldman, S. ; Anderson, W. ; Ashton, R. ; Chaine, M. ; Duvvury, C. ; Maloney, T. ; Worley, E.
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
Abstract :
This paper describes an ESD technology benchmarking strategy for evaluating the ESD robustness of a semiconductor technology. The strategy consists of a set of CMOS “building block” test structures, a matrix of these test structures, electrical characterization parameters, ESD metrics, a standardized failure criteria, and an extraction and testing procedure
Keywords :
CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit reliability; integrated circuit testing; performance evaluation; CMOS building block test structures; CMOS technologies; ESD metrics; ESD robustness; ESD technology benchmarking strategy; benchmarking strategy; electrical characterization parameters; electrostatic discharge; extraction procedure; semiconductor technology; standardized failure criteria; testing procedure; Benchmark testing; CMOS process; CMOS technology; Circuit testing; Electrostatic discharge; Foundries; MOSFETs; Robustness; Semiconductor device testing; Vehicles;
Conference_Titel :
Integrated Reliability Workshop Final Report, 1998. IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-4881-8
DOI :
10.1109/IRWS.1998.745371
