Title :
Exploiting VHDL-RTL features to reduce the complexity of power estimation in combinational circuits
Author :
Machado, Felipe ; Torroja, Yago ; Riesgo, Teresa
Keywords :
Binary decision diagrams; Boolean functions; Capacitance; Circuit simulation; Combinational circuits; Data structures; Energy consumption; Probability; Registers; Signal design;
Conference_Titel :
Research in Microelectronics and Electronics, 2005 PhD
Print_ISBN :
0-7803-9345-7
DOI :
10.1109/RME.2005.1542949
