Title :
Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers
Author :
Chen, C.L. ; Chen, C.K. ; Yost, D.-R. ; Knecht, J.M. ; Wyatt, P.W. ; Burns, J.A. ; Warner, K. ; Gouker, P.M. ; Healey, P. ; Wheeler, B. ; Keast, C.L.
Author_Institution :
Lincoln Lab., Massachusetts Inst. of Technol., Lexington, MA
Abstract :
RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved.
Keywords :
MOSFET circuits; radiofrequency amplifiers; silicon-on-insulator; wafer-scale integration; 3D implementation; MOSFET; conventional 2D layout; silicon-on-insulator RF amplifiers; wafer stacking; wafer-scale 3D integration; CMOS process; CMOS technology; Circuit optimization; Cost function; Delay; Integrated circuit interconnections; Radiofrequency amplifiers; Silicon on insulator technology; Stacking; Wafer scale integration;
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-3940-9
Electronic_ISBN :
978-1-4244-2831-1
DOI :
10.1109/SMIC.2009.4770536
