A 5-Gb/s digitally controlled 3-tap DFE receiver for serial communications

Author

Han, Jae-Duk ; Shin, Woo-Yeol ; Choi, Woo-Seok ; Chun, Jung-Hoon ; Kim, Suhwan ; Jeong, Deog-Kyoon

Author_Institution

TLI Inc., Seongnam, South Korea

fYear

2010

fDate

8-10 Nov. 2010

Firstpage

1

Lastpage

4

Abstract

Decision feedback equalizers (DFEs) play a critical role in high-speed communications through band-limited channels. We implemented a 3-tap DFE receiver for 5-Gb/s data bandwidth. To realize a multi-tap DFE operation, a digital-control scheme is proposed that does not use analog circuits for biasing, such as DACs. In addition to the conventional loop unrolling, several techniques including combined feedback are used to reduce the latency of the feedback path. Fabricated in a 0.13-μm CMOS process, the prototype of the proposed DFE core has an area of 0.009 mm² and consumes 8.4 mW from a 1.2-V supply, achieving a BER of less than 10^-11 over a pair of 28-inch Nelco 4000-6 board traces.

Keywords

CMOS integrated circuits; decision feedback equalisers; digital control; digital-analogue conversion; error statistics; radio receivers; 3-tap DFE receiver; BER; CMOS process; DAC; Nelco 4000-6 board traces; band-limited channels; bit rate 5 Gbit/s; decision feedback equalizers; digital control; high-speed communications; power 8.4 mW; serial communications; size 0.13 mum; size 28 inch; voltage 1.2 V; CMOS integrated circuits; Clocks; Decision feedback equalizers; Delay; Pollution measurement; Power demand; Receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian

Conference_Location

Beijing

Print_ISBN

978-1-4244-8300-6

Type

conf

DOI

10.1109/ASSCC.2010.5716563

Filename

5716563