DocumentCode :
2559426
Title :
On-chip sine-wave noise generator for analog IP noise tolerance measurements
Author :
Soda, Masaaki ; Bando, Yoji ; Takaya, Satoshi ; Ohkawa, Toru ; Takaramoto, Toshiharu ; Yamada, Toshio ; Kumashiro, Shigetaka ; Mogami, Tohru ; Nagata, Makoto
Author_Institution :
MIRAI-Selete, Sagamihara, Japan
fYear :
2010
fDate :
8-10 Nov. 2010
Firstpage :
1
Lastpage :
4
Abstract :
A sine-wave noise generator with a harmonic-eliminated waveform is proposed for measuring the noise tolerance of analog IPs. In the waveform, harmonics up to the thirteenth harmonic are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. This waveform includes only high-region frequency harmonic components which are easily suppressed by a low-order filter. In the circuit, the harmonic-eliminated waveform generator is combined with a current-controlled oscillator and a frequency-adjustment circuit. The sine-wave noise generator can generate power-line noise from 20 MHz to 220 MHz in 1 MHz steps. A spurious-free dynamic range (SFDR) of 45 dB is obtained at the 100 MHz noise frequency.
Keywords :
noise generators; noise measurement; variable-frequency oscillators; waveform generators; analog IP; current-controlled oscillator; frequency harmonic components; harmonic-eliminated waveform; low-order filter; noise tolerance measurements; on-chip sine-wave noise generator; rectangular waves; Conferences; Solid state circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
Type :
conf
DOI :
10.1109/ASSCC.2010.5716573
Filename :
5716573
Link To Document :
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