Title :
Design of a discrete cosine transform circuit using the residue number system
Author :
Wrzyszcz, Artur ; Caban, Dariusz ; Dagless, Erik L.
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Bristol, UK
Abstract :
The design of an integrated circuit aimed at efficient discrete cosine transform computation is presented. High performance is obtained through the use of pipelining and residue arithmetic. An approach to high-speed modular multiplication employing the periodic properties of powers of two taken modulo A is reported. The test chip is implemented using the ES2 1.5-μm CMOS process, has a die size of 29.55 mm2 and dissipates 140 mW of power. The maximum throughput is in excess of 30 MHz
Keywords :
CMOS digital integrated circuits; circuit CAD; digital signal processing chips; discrete cosine transforms; image coding; integrated circuit design; pipeline arithmetic; residue number systems; 1.5 micron; 140 mW; CAD IC design; CMOS process; DSP chip; discrete cosine transform circuit; high-speed modular multiplication; image compression; maximum throughput; periodic properties; pipelining; powers of two taken modulo A; residue arithmetic; residue number system; Arithmetic; CMOS process; Circuits; Computer architecture; Digital signal processing; Discrete cosine transforms; Hardware; Testing; Throughput; Very large scale integration;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386412
