The U1traSPARC T1: A Power-Efficient High-Throughput 32-Thread SPARC Processor

Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power and cooling in today\´s data centers. The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture, which combines eight 4-threaded 64 b cores, a high bandwidth interconnect crossbar, a shared 3 MB L2 Cache and four double-width DDR2 DRAM interfaces. Implemented in 90 nm CMOS technology, the 378 mm² die consumes only 63 W at 1.2 GHz. The UltraSPARC Tl based systems are oriented to a wide variety of applications, including WebServers, data and application servers, Java applications, search, streaming video and Telco applications.