An approach to scheduling and allocation using regularity extraction

The authors propose that an important class of VLSI systems that are characterized by regularity of their descriptions can be efficiently synthesized in a hierarchical fashion. In other words, the regularity can be extracted to abstract the system design, thereby simplifying the complex tasks of behavioral synthesis. Heuristics that extract regularity and explore the design space in a hierarchical fashion are presented and the feasibility of the approach on signal processing systems is demonstrated. Extension of the proposed approach to other synthesis tasks is being investigated