A 10b 320MS/s self-calibrated pipeline ADC

A high-speed low-power self-calibrated pipeline ADC is presented. Gain error due to low-gain opamp used in multiplying DAC (MDAC) is corrected by the proposed foreground calibration technique. It adjusts the inter-stage gain by connecting a calibration capacitor into the MDAC positive feedback path. It only requires 168 clock cycles to complete the calibration without external precise references. The calibration circuit does not consume power during normal conversion. The prototype ADC in 90 nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 dB and 54.2dB. The total power dissipation is 42 mW and it occupies an active chip area of 0.21 mm² Its figure-of-merit (FOM) is 442 fJ/conversion-step.