• DocumentCode
    256044
  • Title

    Effect of parallelization on conditional summation

  • Author

    Pradhan, S. ; Kumar, S. ; Patle, V.K.

  • Author_Institution
    SoS in Comput. Sci. & IT, Pt. Ravishankar Shukla Univ., Raipur, India
  • fYear
    2014
  • fDate
    11-13 Dec. 2014
  • Firstpage
    330
  • Lastpage
    333
  • Abstract
    If statement´ is vectorization inhibiter that is prevents vectorization. But if statement is not parallelization inhibiter that is it allows parallelization. We take a problem in which conditional if statement is applied for addition of numbers of 2 series or arrays after multiplication. We measure time for addition of multiplication of series under certain condition, when ordinary sequential method is applied. Secondly we divide the entire problem into certain number of equal parts (Threads) and perform addition on different cores. Then we compute the speedup and other parameters.
  • Keywords
    parallel processing; vectors; conditional summation; parallelization effect; vectorization inhibiter; Computers; Educational institutions; Grid computing; Inhibitors; Instruction sets; Parallel processing; OpenMP; Parallel Computing component; Parallelization; Threads; Vectorization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel, Distributed and Grid Computing (PDGC), 2014 International Conference on
  • Conference_Location
    Solan
  • Print_ISBN
    978-1-4799-7682-9
  • Type

    conf

  • DOI
    10.1109/PDGC.2014.7030765
  • Filename
    7030765