A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS

Author

Fang, David ; Roberts, Ryan ; Nikolic, Borivoje

Author_Institution

Univ. of California, Berkeley

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

423

Lastpage

426

Abstract

A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.

Keywords

CMOS memory circuits; DRAM chips; digital-analogue conversion; low-power electronics; photolithography; CMOS technology; analog DRAM; capacitive process mismatch; charge leakage; data hold time; digital-to-analog converter; maskless lithography interface; mixed-signal interface; self-calibrating compensation circuit; size 2 mm; size 3 mum; size 90 nm; voltage 1 V to 2.5 V; word length 6 bit; CMOS process; CMOS technology; Costs; Lithography; Mirrors; Optical modulation; Prototypes; Random access memory; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357941

Filename

4197680