Methodology to design SATA 3.0 channels with re-driver

As signal speeds continue to increase, maintaining signal quality has become a greater challenge for signal integrity (SI) engineers. Migrating a system to a next-generation interface technology operating at higher speeds brings with it increased sensitivity to attenuation and jitter that can severely curtail reach and reliability. In order to meet the interface specification, expensive choices such as low loss material and expensive connectors are needed. Addition of re-drivers to a channel is becoming a popular and relatively in-expensive solution to enhance SI performance. The selection of re-drivers presents some of design and simulation challenges over high speed channels. This paper describes a methodology which enables SI engineers to effectively simulate a SATA 3.0 channel with re-drivers. The proposed methodology is further implemented in one of the server systems to evaluate the data correctness for re-driver usage in the high speed SATA channel. Simulation and measurement data are correlated to validate the effectiveness of re-driver simulation. A Design of Experiment (DoE) is created to address the simulation challenges and accuracy of the simulation result. DoE also addresses the statistical analysis to understand the re-driver parameters that impact eye diagram and jitter. Design engineers can use the flow and methodology introduced in this paper to evaluate channel performance for High Volume Manufacturing (HVM) for their proposed topology.