Impact of sockets in Package-On-Package electrical validation & design considerations

For next generation mobile tablet platforms, cost and form factor, power and performance are the key vectors which lead to design wins. SoCs(System-On-Chip) are fast becoming the solution for these platforms which contain most of the interfaces in a single package. To reduce power and real estate the trend is to design denser SoC packages which has further led to many PoP (Package-On-Package) designs. These PoP designs are gaining momentum, which give premium tablets with low power, reduced real estate, higher speed and better performance. But these designs come with its own challenges especially on the system and electrical validation side. For example any debugging of system memory interface needs access to memory signals which is all concealed in a PoP now. This led to the use of different kind of sockets and validation cards, which can give access to needed signals. Sockets are again important for volume characterization of SoC or memory parts as well. This raises few interesting questions:- at higher speeds are sockets reliable? Do sockets alter the electrical behavior of a particular interface? If yes, how much it will alter? Do we have different variables to tune the socket behavior? Can we predict the socket impact and manipulate the data? In this paper we try to answer these important questions with simulation and lab data, based on an Intel platform with special emphasis on system memory interface.