Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology

Author

Ortolland, C. ; Ragnarsson, L. -Å ; Kerner, C. ; Chiarella, T. ; Rosseel, E. ; Okuno, Y. ; Favia, P. ; Richard, O. ; Everaert, J.-L. ; Schram, T. ; Kubicek, S. ; Absil, P.P. ; Biesemans, S. ; Schreutelkamp, R. ; Hoffmann, T.

Author_Institution

IMEC, Leuven, Belgium

fYear

2009

fDate

11-12 June 2009

Firstpage

54

Lastpage

57

Abstract

In this paper, we have done a comprehensive study of the junction anneal strategy (by spike and/or laser) for advanced technology nodes with Hk/MG and high-k capping film to control the eWF. It has been shown that a low long channel Vth is easily achievable with anneal sequence optimization. In particular with the help of laser which creates more dipoles for NMOS case with La-based capping. But also on PMOS due to a lower thermal budget which permits to avoid eWF modulation penalty for thin EOT. Good device scalability gain has been also achieved (10 and 15 nm for respectively NMOS and PMOS) with the sequence optimization without performance degradation.

Keywords

CMOS integrated circuits; high-k dielectric thin films; laser beam annealing; La-based capping; NMOS; PMOS; advanced high-k CMOS technology; eWF modulation penalty; high-k capping film; junction anneal sequence optimization; laser beam annealing; laser spike annealing; metal gate CMOS technology; Annealing; CMOS technology; Dielectric substrates; High K dielectric materials; High-K gate dielectrics; MOS devices; Optical control; Optical materials; Scalability; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2009. IWJT 2009. International Workshop on

Conference_Location

Kyoto

Print_ISBN

978-1-4244-3319-3

Electronic_ISBN

978-1-4244-3320-9

Type

conf

DOI

10.1109/IWJT.2009.5166219

Filename

5166219