Title :
Fabrication of through-wafer interconnections by gold electroplating
Author :
Vasilache, D. ; Colpo, S. ; Giacomozzi, F. ; Margesin, B. ; Chistè, M.
Author_Institution :
FBK-irst Trento, Trento, Italy
Abstract :
A new method for conductive via´s using gold electroplating is presented. Tapered walls through wafer via (TWV) holes were made using a variable isotropy DRIE process, with a very good control over the obtained angles - angles of 11.3° and 21.8° were obtained with errors smaller than 10%. Barrier and seed layers were deposited in via´s performed by PVD (Physical Vapor Deposition) techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via´s.
Keywords :
electroplating; gold; interconnections; vapour deposition; Au; DRIE process; gold electroplating; physical vapor deposition; tapered walls; through wafer interconnection; through wafer via holes; Adaptive optics; Etching; Gold; Manufacturing; Optical attenuators; Optical films; Shape; DRIE; gold electroplating; through silicon via; variable isotropy process;
Conference_Titel :
Semiconductor Conference (CAS), 2011 International
Conference_Location :
Sinaia
Print_ISBN :
978-1-61284-173-1
DOI :
10.1109/SMICND.2011.6095746