Title :
Area and power analysis of AES using hardware and software Co-design
Author :
Deotare, V.V. ; Padole, D.V. ; Wakode, A.S.
Author_Institution :
GHRCE Nagpur, Nagpur, India
Abstract :
This paper investigate the analysis of power and area of Advanced Encryption Standard (AES) algorithm using different design tool like ARM based, Hardware (VHDL/Verilog) and HW/SW. Results of area and power consumption for different design are varying and the percentage improvement in the power and area is marginable.The power improvement range is between 22.5% to 90% and the area improvement range is between 5% to 30%. The proposed AES is implemented on different hardware like ARM, microblaze processor and FPGA.
Keywords :
cryptography; hardware-software codesign; power consumption; AES; ARM based tool; Advanced Encryption Standard algorithm; FPGA; HW/SW; VHDL; Verilog; area analysis; hardware-software co-design; microblaze processor; power analysis; power consumption; Algorithm design and analysis; Ciphers; Encryption; Hardware; Power demand; Registers; Software; Decryption Plain text; Encryption; FPGA; Substitution; Time evaluation; cipher text; key operating frequency;
Conference_Titel :
Wireless Computing and Networking (GCWCN), 2014 IEEE Global Conference on
Conference_Location :
Lonavala
DOI :
10.1109/GCWCN.2014.7030877
