DocumentCode :
2563518
Title :
Dynamic power analysis for custom designs
Author :
Bijansky, Stephen ; Mohd, Bassam ; Mohammad, Baker
Author_Institution :
Qualcomm, Austin, TX, USA
fYear :
2009
fDate :
18-20 May 2009
Firstpage :
173
Lastpage :
176
Abstract :
This work uses switch-level Verilog to simulate entire benchmarks using transistor level schematics and post-layout capacitance extraction. By translating a schematic netlist into a transistor level Verilog netlist, thousands of benchmark cycles can be simulated in minutes or hours compared with only tens of cycles using a fast spice simulator. This difference in simulation speed enables simulating an entire benchmark instead of trying to guess what a good spice simulation window is. This flow has been used extensively for power estimation and optimization of custom-based cache designs integrated into Qualcomm´s 45 nm low power DSPs.
Keywords :
SPICE; hardware description languages; custom design; custom-based cache design; dynamic power analysis; fast spice simulator; optimization; post-layout capacitance extraction; power estimation; schematic netlist; simulation speed; spice simulation window; switch-level Verilog; transistor level Verilog netlist; transistor level schematics; Analytical models; Benchmark testing; Capacitance; Clocks; Hardware design languages; Logic; Power generation; Process design; Runtime; Voltage; VLSI design; Verilog simulation; activity factor; power estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-2933-2
Electronic_ISBN :
978-1-4244-2934-9
Type :
conf
DOI :
10.1109/ICICDT.2009.5166289
Filename :
5166289
Link To Document :
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