48 MHz clock generating system for USB 2.0 with enhanced bandgap reference

Author

Yoo, SeungTaek ; Kim, Seok ; Chun, Jung-Hoon ; Kwon, Kee-Won ; Jun, Young-Hyun

Author_Institution

Semicond. Div., Samsung Electron., Yongin, South Korea

Volume

2

fYear

2011

fDate

17-19 Oct. 2011

Firstpage

409

Lastpage

412

Abstract

A clock generating system for USB 2.0 with an enhanced bandgap reference circuit is proposed to replace an external crystal oscillator. To comply with clock frequency and long term jitter specifications under high supply noise, the power supply of the DCO is regulated by a low drop-out regulator. The reference voltage for the LDO is generated by the bandgap reference circuit with two bandgap cores to achieve high PSRR. The proposed clock generating system implemented in a 130nm CMOS process shows ±2.5ns jitter under ±400mV supply noise.

Keywords

CMOS digital integrated circuits; crystal oscillators; energy gap; jitter; reference circuits; system buses; voltage regulators; CMOS process; DCO; PSRR; USB 2.0; clock frequency; clock generating system; enhanced bandgap reference circuit; external crystal oscillator; frequency 48 MHz; high supply noise; long term jitter specification; low drop-out regulator; power supply; size 130 nm; Clocks; Jitter; Noise; Oscillators; Photonic band gap; Switches; Universal Serial Bus; BGR; DCO; LDO; USB; bandgap reference;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference (CAS), 2011 International

Conference_Location

Sinaia

ISSN

1545-827X

Print_ISBN

978-1-61284-173-1

Type

conf

DOI

10.1109/SMICND.2011.6095832

Filename

6095832