A Novel Architecture for the Computation of the 2D-DWT

This paper proposes a new approach for the design of hardware architecture for the computation of 2D-DWT for an 8 x 8 image. The key feature of this design is to directly apply 2D-DWT on alternate pixels of an image, called as the Non-Separable method, and implement it on an FPGA. The resulting design was implemented using only 6 adders and 10 multipliers, thus optimizing the number of multipliers and adders required for the computation of 2D-DWT. Thus our approach provides a cost effective solution as compared to the conventional 2D non-separable methods without compromising on speed performance. The design is implemented on Xilinx Virtex II Pro FPGA development kit and synthesized using Xilinx XST (VHDL/Verilog) synthesis tool. Key terms: 2D-DWT, Signal Processing, VLSI, FPGA, filter coefficients, IDWT.