A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture

Author

Hirose, Tatsuya ; Kuriyama, H. ; Murakami, Shinsuke ; Yuzuriha, K. ; Mukai, Toshiharu ; Tsutsumi, Koji ; Nishimura, Yasutaro ; Kohno, Yusuke ; Anami, K.

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

132

Lastpage

133

Abstract

A 20-ns, 4-Mb CMOS SRAM with both 4 M*1 and 1M*4 organizations and fabricated using a quadruple-polysilicon, double-metal, twin-well 0.6- mu m CMOS process technology is described. A word-decoding architecture and a sensitive sense amplifier, combined with an address transition detector (ATD) technique, realize high-speed, low-power operation. Because conventional divided-word-line (DWL) structure cannot realize the high-speed and low-power word decoding in megabit SRAMs, hierarchical word decoding (HWD) is utilized. The RAM has a fast address mode using the 16-b parallel data bus scheme.<>

Keywords

CMOS integrated circuits; SRAM chips; decoding; 0.6 micron; 16-b parallel data bus scheme; 20 ns; 4 Mbit; CMOS SRAM; CMOS process technology; address transition detector; double-metal; fast address mode; hierarchical word decoding architecture; high-speed; low-power operation; quadruple-polysilicon; sense amplifier; static RAM; twin-well; CMOS process; CMOS technology; Capacitance; Decoding; Detectors; MOS devices; OWL; Random access memory; Read-write memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110162

Filename

110162