Enhanced implementation of morphological operators on a synthesizable ASIP

Author

Haggui, Souhail ; Debbabi, Imen ; Tlili, Fethi

Author_Institution

GRES´COM Lab., Ecole Suprieure des Commun. de Tunis (SUP´COM), Tunis, Tunisia

fYear

2014

fDate

14-16 April 2014

Firstpage

1124

Lastpage

1128

Abstract

Mathematical morphology operators are applied in many real time applications such as computer vision. Therefore, an efficient hardware implementation is needed to satisfy these real time requirements. In this paper we present an ASIP for basic morphological operations. We propose a modification of HGW algorithm to deal with the Plasma Soft Core processor. The ASIP has been synthesized into a FPGA. It has therefore achieved a high frequency of 137 MHz and processed a speed of 2.88ms with a flat structuring element.

Keywords

computer vision; field programmable gate arrays; mathematical morphology; microprocessor chips; real-time systems; FPGA; HGW algorithm; computer vision; flat structuring element; frequency 137 MHz; hardware implementation; mathematical morphology operators; plasma soft core processor; real time applications; synthesizable ASIP; van Herk Gill Werman algorithm; Computer architecture; Hardware; Image processing; Merging; Morphology; Plasmas; Shape; ASIP; FPGA; HGW; Mathematical Morphology; Plasma Soft Core;

fLanguage

English

Publisher

ieee

Conference_Titel

Multimedia Computing and Systems (ICMCS), 2014 International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4799-3823-0

Type

conf

DOI

10.1109/ICMCS.2014.6911408

Filename

6911408