Title :
A 50 ns 16 Mb DRAM with a 10 ns data rate
Author :
Kalter ; Barth, Jens ; Dilorenzo, J. ; Drake, C. ; Fifield, J. ; Hovis, W. ; Kelley, G. ; Lewis, Simon John Geoffrey ; Nickel, J. ; Stapper, C. ; Yankosky, J.
Author_Institution :
IBM Gen. Technol. Div., Essex Junction, VT, USA
Abstract :
A 16-Mb DRAM chip fabricated in a 0.5- mu m CMOS process using silicided polysilicon, double metal, and trench storage is described. It incorporates an architecture that supports either 11/11 or 12/10 RAS/CAS (row-address strobe/column-address-strobe) addressing. It is segmented to utilize bit redundancy of 2 lines/137-b lines/half quadrant, and separate word-redundant array of 24 lines/quadrant, providing any-for-any-word-line replacement within a quadrant. It has single-error-correct/double-error-detect (SEC/DED) error checking and correcting (ECC) Hamming odd-weight code/quadrant and either 5-V or 3-V operation. The design provides a RAS access of 50 ns with 16-ns fast-page access, 18-ns static column or toggle of 10 ns at 2.9 V and 85 degrees C. DRAM features are summarized.<>
Keywords :
CMOS integrated circuits; DRAM chips; error correction codes; 10 ns; 50 ns; CMOS process; DRAM; Hamming odd-weight code/quadrant; RAS/CAS addressing; bit redundancy; data rate; double metal; error checking; error correction; fast-page access; polysilicon; single-error-correct/double-error-detect; static column; trench storage; word-redundant array; Content addressable storage; Decoding; Delay; Error correction codes; Logic design; Nickel; Packaging; Random access memory; Redundancy; Switches;
Conference_Titel :
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1990.110210
