A power optimized carry generation logic Implementation using input pattern based area reduction technique for Adder Structures

In this paper, we present a novel carry break addition, which exploits certain aspects of carry generation & manipulation based on the bit positions of input vectors. It takes a design methodology into consideration while implementing it in lesser area without sacrificing the performance in terms of speed and power. Selective use of certain circuit structures and transistor sizing are carefully done to result in low power design. Depending on input vectors, it shows high speed carry generation with worst-case delay of 3.23 ns for four-bit adder slice. Considering the layout regularity and circuit topology, it has been integrated into an area of 8871 mum² in 1.2 um 5 V SCL CMOS technology. Exploiting the behavior of bit-slice architectures, 32 b MCBA Macrocell has also been designed and implemented using these four-bit slices.