DocumentCode
2567487
Title
A 65nm low-power embedded DRAM with extended data-retention sleep mode
Author
Nagai, Takayuki ; Wada, Masaki ; Iwai, Hisato ; Kaku, Masanori ; Suzuki, A. ; Takai, Toshiaki ; Itoga, N. ; Miyazaki, Toshimasa ; Takenaka, Hikaru ; Hojo, Toshiaki ; Miyano, S.
Author_Institution
Toshiba, Kawasaki
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
567
Lastpage
576
Abstract
An extended data retention (EDR) sleep mode with ECC and MT-CMOS is proposed for embedded DRAM power reduction. In sleep mode, the retention time improves by 8 times and the leakage current is reduced to 13% of the normal operation mode. Since ECC scrubbing operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low-power embedded DRAM macro featuring 400MHz operation and 0.39mW of data-retention power is realized
Keywords
CMOS memory circuits; DRAM chips; embedded systems; leakage currents; low-power electronics; nanoelectronics; 0.39 mW; 400 MHz; 65 nm; ECC; MT-CMOS; extended data retention sleep mode; leakage current; low power embedded DRAM; Bandwidth; Circuits; Degradation; Error correction; Error correction codes; Leakage current; Logic; Random access memory; Redundancy; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696093
Filename
1696093
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