Title :
A high-speed dual field arithmetic unit and hardware implementation
Author :
Wang, Jian ; Jiang, Anping
Author_Institution :
Peking Univ., Beijing
Abstract :
Finite fields have been used for many types of public key cryptography, such as elliptic curve (EC) and RSA cryptosystems. This paper presents an arithmetic unit that support Galois fields GF(p) and GF(2m) for arbitrary prime numbers and irreducible polynomials respectively. The arithmetic unit can do the Galois field arithmetic operations of addition, subtraction, multiplication, squaring, inversion and division. The least significant bit first (LSB-first) scheme for modular multiplication and the extended Euclid´s algorithm for modular inversion are both modified for the arithmetic unit. The architecture has been implemented using 0.18-mum CMOS standard cell library, the clock frequency can reach at least 250 MHz for a 256-bit arithmetic unit. Furthermore, any bit length can be supported by any hardware configuration so long as the memory capacity is sufficient.
Keywords :
CMOS integrated circuits; Galois fields; VLSI; adders; digital arithmetic; polynomials; CMOS standard cell library; Euclid´s algorithm; Galois field arithmetic operations; arbitrary prime numbers; dual field arithmetic unit; hardware implementation; irreducible polynomials; least significant bit first scheme; modular multiplication; word length 256 bit; Arithmetic; Clocks; Elliptic curve cryptography; Elliptic curves; Frequency; Galois fields; Hardware; Libraries; Polynomials; Public key cryptography; Elliptic Curve; Galois fields; Public Key Cryptography; RSA; VLSI implementation.;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415605