DocumentCode
2568068
Title
A 13b linear 40MS/s pipelined ADC with self-configured capacitor matching
Author
Ray, Sambaran ; Bang-Sup Song
Author_Institution
California Univ., San Diego, CA
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
852
Lastpage
861
Abstract
Using statistical matching properties of capacitor arrays, a pipelined ADC self-configures the MDAC capacitor array for best matching from many trial combinations. A 0.18mum CMOS prototype achieves 13b linearity and over 80dB SFDR at 43MS/s. The chip consumes 268mW from a 1.8V supply and occupies 3.6mm2
Keywords
CMOS integrated circuits; analogue-digital conversion; capacitors; pipeline processing; 0.18 micron; 1.8 V; 13 bit; 268 mW; CMOS prototype; pipelined ADC; self-configured capacitor matching; statistical matching; CMOS process; Calibration; Error correction; MIM capacitors; Measurement standards; Measurement techniques; Resistors; Sampling methods; Space exploration; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696125
Filename
1696125
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