A high efficient analog charge delay line for high performance CMOS readout integrated circuits with TDI function

A high efficient analog charge delay line (ACDL) is proposed in this paper. We can use these analog delay lines to realize high performance CMOS readout integrated circuits (ROIC) with time delay integration (TDI) function. A CMOS ROIC for 288 times 4 IRFPA were designed, manufactured, and tested. The chip has 4 video outputs, whose pixel frequency is 4~5MHz (for 384 times 288 format, its frame frequency can achieve 160 Hz). Test results show this chip has high dynamic range (>78 dB), high linearity (>99.5%), and high uniformity (96.8%). (TDI) function.