Investigation of Gate Length Effect on SOI-MOSFET Operation

In this paper the effect of the gate length on the operation of SOI-MOSFETs is evaluated via simulations. Three transistors with gate lengths 100, 200 and 500 nm are simulated. Simulations show that with a fixed channel length, when the gate length is increased, the curve slope ID-VGS is increased, and therefore the transistor trans-conductance increases. Moreover, with increasing the gate length, the effect of the drain voltage on the drain current is reduced, which results in decreasing of the drain induced barrier lowering (DIBL).