• DocumentCode
    2569934
  • Title

    An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS

  • Author

    Hsu, Steven ; Agarwal, Amit ; Anders, Mark ; Mathew, Sanu ; Krishnamurthy, Ram ; Borkar, Shekhar

  • Author_Institution
    Intel, Hillsboro, OR
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    1785
  • Lastpage
    1797
  • Abstract
    A 16times64b 1R/1W register file is fabricated in 65nm CMOS technology. The 0.017mm2 chip performs 8.8GHz fused decode and read/write operations in a single cycle while dissipating 198mW at 1.2V, 50degC, with frequency scalable to 10.1GHz at 1.4V, 50degC. Variation-tolerant keeper compensation, leakage-tolerant BL/WL architecture and optimal non-minimum channel-length usage enable wide PVT operating range with an active leakage of 25mW and a BL noise droop les8mV
  • Keywords
    CMOS digital integrated circuits; microprocessor chips; 1.2 V; 1.4 V; 10.1 GHz; 193 mW; 1R/1W register file; 25 mW; 50 C; 65 nm; 8.8 GHz; BL/WL architecture; CMOS technology; leakage-tolerant architecture; optimal nonminimum channel-length; read/write operations; variation-tolerant keeper compensation; variation-tolerant register file; Active noise reduction; CMOS technology; Clocks; Decoding; Delay; Inverters; MOS devices; Noise measurement; Power measurement; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696235
  • Filename
    1696235
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2569934