Digital decimation filter design and simulation for delta-sigma ADC with high performance

This paper study a kind of design method about the digital decimation filter design for delta-Sigma ADC with high performance and validated it by simulation using MATLAB tool. A 16-bit digital decimation filter design for stereo audio delta-sigma ADC has been developed. A two-stage decimation filter architecture which can reduce digital switching noise was also introduced in this design. A merged four-stage comb filter is used for the first stage, and a bit-serial finite-impulse-response (FIR) filter is used for the second stage. In addition, a high pass filter is used to compensate filter´s DC offset. The design simulated using MATLAB according to this scheme can achieve higher performances.