A novel low power bus coding technique for nanometer technology

The power dissipation on data bus is becoming a significant contributor to total power dissipation of nanometer CMOS circuits. As technology scales, the inter-wire capacitance increases greatly. The power consumed on inter-wire capacitance exceeds on the grounded capacitance. In this paper, a new low power data bus coding technology is introduced which considers the inter-wire capacitance sufficiently. This method can be achieved with less hardware and the power dissipation can be reduced by 32.1% for 32-bit bus.