Title :
A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS
Author :
Khellah, Muhammad M. ; Nam Sung Kim ; Howard, John ; Ruhl, G. ; Yibin Ye ; Tschanz, James ; Somasekhar, Dinesh ; Borkar, N. ; Hamzaoglu, Fatih ; Pandya, G. ; Farhang, Arman ; Zhang, Kai ; De, Vivek
Author_Institution :
Intel, Hillsboro, OR
Abstract :
An SRAM macro, implemented in a 65nm CMOS process, uses a dual supply to maximize density while enabling the use of low voltage for the processor core. Measurements of a 256kb block show 4.2GHz operation using 29mW from 1.2V at 85degC, with core logic operating down to 0.7V and a sleep biasing scheme that autonomously compensates for PVT and aging
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; 1.2 V; 256 kbytes; 29 mW; 4.2 GHz; 65 nm; 85 C; CMOS process; SRAM building block; core logic; processor core; Aging; CMOS technology; Clamps; Delay; Energy efficiency; Frequency; Leakage current; Random access memory; Sleep; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696323
