Title :
A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth
Author :
Tseng, Chih ; Kim, Jae-Hyeong ; Chen, Suzanne ; Huang, Mu-Hsiang ; Lu, Chungji ; Hashiguchi, Ikuo ; Miyazima, Yoshifumi ; Ichihashi, Masahiro ; Maki, Kentaro ; Nakashima, Katsuya ; Chuang, Patrick
Author_Institution :
Sony Electron., San Jose, CA
Abstract :
A 72Mb 6T SRAM is designed with 2times144 separate-I/O and random R/W in parallel per cycle running at 875MHz DDR to achieve 504Gb/s bandwidth. It is fabricated in a 90nm CMOS process. Dual R/W self-timed clocks with core emulators are multiplexed to operate the SRAM core at 875MHz. On-chip DLL, programmable I/O skews, and programmable input termination and output driver impedance with precise linearity are essential for this 504Gb/s interface
Keywords :
CMOS integrated circuits; SRAM chips; delay lock loops; integrated circuit design; 504 Gbit/s; 72 MBytes; 90 nm; CMOS process; core emulators; data bandwidth; on-chip delay locked loop; programmable I/O skews; programmable input termination; separate-I/O SRAM chip; synchronous SRAM chip; Bandwidth; CMOS process; Circuits; Clocks; Power generation; Random access memory; SRAM chips; Signal design; Signal processing; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696324
