DocumentCode :
2572376
Title :
A watermarking technique for hard IP protection in post-layout design level
Author :
Cai, Xueyu ; Gao, Zhiqiang ; Bai, Fujun ; Xu, Yi
Author_Institution :
Tsinghua Univ., Beijing
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
1317
Lastpage :
1320
Abstract :
The intellectual property (IP)-reuse-based SOC design methodology has become the mainstream. However malice modification of IP is badly infringing the expansion of legal IP- trade. Consequently the IP copyright protection becomes very sensitive and urgent. Among all kinds of IP protection (IPP) techniques, the watermarking is one of the most developed and promising approaches. In this paper we introduce a new watermarking technique for hard IP protection by embedding additional design constraints in post-physical layout design level. It can be applied to both VLSI designs and full-custom designs. In this paper, we focus on the application of this IPP approach in full-custom ones. The principle and a watermarking implementation system are proposed, and the experimental results are reported.
Keywords :
VLSI; copyright; industrial property; integrated circuit layout; system-on-chip; watermarking; SOC design methodology; VLSI designs; copyright protection; full-custom designs; intellectual property; post-layout design level; watermarking technique; Copyright protection; Design methodology; Law; Legal factors; Microelectronics; Process design; Scattering; Time to market; Very large scale integration; Watermarking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415879
Filename :
4415879
Link To Document :
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