DocumentCode :
2572467
Title :
Clock tree synthesis for low power and low susceptibility to variation
Author :
Cheon, Yongseok ; Ho, Pei-Hsin ; Hou, Wenting ; Liu, Yi ; Wang, Dong
Author_Institution :
Synopsys, Inc., Sunnyvale
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
1333
Lastpage :
1333
Abstract :
Power is one of the biggest concerns of IC designs today. For consumer electronics the energy consumption of the ICs limits the time between charging the batteries. For high-frequency computers the power density of the ICs limits the performance of the ICs. Clock distribution networks typically contribute more than one third of the total power consumption, including both leakage and dynamic power consumption.
Keywords :
clocks; consumer electronics; electronic design automation; integrated circuit design; low-power electronics; power aware computing; CoolFire projects; IC designs; clock distribution networks; clock tree synthesis; consumer electronics; design automation tools; energy consumption; Batteries; Clocks; Consumer electronics; Energy consumption; High performance computing; Integrated circuit synthesis; Network synthesis; Network topology; Storms; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415884
Filename :
4415884
Link To Document :
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