DocumentCode :
2572847
Title :
Modeling on-chip communication
Author :
Seceleanu, Tiberiu ; Plosila, Juha
Author_Institution :
Dept. of Inf. Technol., Turku Univ., Finland
fYear :
2003
fDate :
19-21 Nov. 2003
Firstpage :
89
Lastpage :
92
Abstract :
Utility of formal methods in hardware design became of crucial importance during the last decade. In this study, we apply techniques of the action systems framework in the development of a bus-based system. The emphasis is on the extraction of the arbiter unit, from an initial high abstract level description.
Keywords :
digital circuits; network synthesis; network topology; system buses; system-on-chip; action systems framework; arbiter unit extraction; bus-based system; formal methods; hardware design; high abstract level description; on-chip communication modeling; Artificial intelligence; Communication channels; Data mining; Design methodology; Digital systems; Hardware; Information technology; Master-slave; Reactive power; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip, 2003. Proceedings. International Symposium on
Print_ISBN :
0-7803-8160-2
Type :
conf
DOI :
10.1109/ISSOC.2003.1267724
Filename :
1267724
Link To Document :
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