DocumentCode :
2573028
Title :
Impact of crosstalk on delay time and a hierarchy of interconnects
Author :
Yamashita, K. ; Odanaka, S.
Author_Institution :
ULSI Process Technol. Dev. Center, Matsushita Electron. Corp., Kyoto, Japan
fYear :
1998
fDate :
6-9 Dec. 1998
Firstpage :
291
Lastpage :
294
Abstract :
Impact of crosstalk on delay time and a hierarchy of interconnects is clarified. The delay time increase is induced by the almost same phenomenon as the crosstalk noise in short interconnects. For global interconnects, the delay time increase by crosstalk is enhanced and hence the delay time improvement trades off between the reduction of the lateral capacitance and the increase of wiring resistance. A multilevel interconnect scheme at each technology generation is further investigated considering the crosstalk effect. Delay time improvements by circuit techniques are discussed to reduce the delay time increase by crosstalk.
Keywords :
crosstalk; delays; integrated circuit interconnections; integrated circuit noise; crosstalk noise; delay time; lateral capacitance; multilevel interconnect; wiring resistance; CMOS logic circuits; Capacitance; Crosstalk; Delay effects; Integrated circuit interconnections; Logic circuits; Signal design; Threshold voltage; Ultra large scale integration; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-4774-9
Type :
conf
DOI :
10.1109/IEDM.1998.746357
Filename :
746357
Link To Document :
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