Shared tungsten structures for FEOL/BEOL compatibility in logic-friendly merged DRAM

Author

Drynan, J.M. ; Fukui, K. ; Hamada, M. ; Inoue, K. ; Ishigami, Takashi ; Kamiyama, S. ; Matsumoto, A. ; Nobusawa, H. ; Sugai, K. ; Takenaka, M. ; Yamaguchi, H. ; Tanigawa, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

849

Lastpage

852

Abstract

Shared tungsten structures are proposed to replace the conventional Si-based structures of commodity DRAMs, thereby enabling alignment with the Logic frontand back-end-of-line processes to achieve full compatibility for sub-quarter-micron merged DRAM-Logic devices. W-based damascene bit lines, storage capacitors, and contact plugs used in the memory cells can be shared as local interconnect lines and stacked via plugs in the Logic circuitry. Adopting bilayer (PVD+CVD) W can realize a 40-65% reduction in interconnect resistance, in addition to its optimal use in Ta/sub 2/O/sub 5/-dielectric full metal capacitors.

Keywords

DRAM chips; integrated circuit interconnections; integrated logic circuits; tungsten; 0.25 micron; BEOL process; FEOL process; Ta/sub 2/O/sub 5/ dielectric full metal capacitor; W; bilayer PVD-CVD W; contact plug; damascene bit line; interconnect resistance; memory cell; merged DRAM-logic device; shared tungsten structure; stacked via plug; storage capacitor; Capacitors; Contact resistance; Electrodes; Etching; Logic devices; Plugs; Random access memory; Temperature; Thermal resistance; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746488

Filename

746488