The origin of secondary electron gate current: a multiple-stage Monte Carlo study for scaled, low-power flash memory

Author

Kencke, D.L. ; Wang, X. ; Wang, H. ; Ouyang, Q. ; Jallepalli, S. ; Rashed, M. ; Maziar, C. ; Tasch, A., Jr. ; Banerjee, S.K.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

889

Lastpage

892

Abstract

A multiple-stage simulation procedure identifies, for the first time, the location of secondary electrons that very efficiently produce gate currents in flash EEPROMs. The simulation method incorporates both electron and hole Monte Carlo analysis to calculate this secondary electron gate current without introducing additional fitting parameters. (I/sub g//I/sub d/) continues to increase for smaller channel length (50/spl times/ from L/sub g/-03.39 to 0.12 /spl mu/m) and higher substrate doping (more than 6/spl times/ when doubled) in scaled, low-power flash memory.

Keywords

Monte Carlo methods; circuit simulation; flash memories; integrated circuit modelling; low-power electronics; semiconductor doping; 0.12 to 0.39 micron; channel length; low-power flash memory; multiple-stage Monte Carlo study; secondary electron gate current; simulation procedure; substrate doping; Charge carrier processes; Discrete event simulation; Doping; EPROM; Electrons; Flash memory; Impact ionization; Microelectronics; Monte Carlo methods; Probability distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746497

Filename

746497