0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology

Author

Ohguro, T. ; Naruse, H. ; Sugaya, H. ; Kimijima, H. ; Morifuji, E. ; Yoshitomi, T. ; Morimoto, T. ; Momose, H.S. ; Katsumata, Y. ; Iwai, H.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

927

Lastpage

930

Abstract

We introduce a 0.12 /spl mu/m nMOS technology with multi-Vth´s for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 /spl mu/m nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design. High Idrive/Ioff ratio for drain current was also realized.

Keywords

CMOS integrated circuits; high-speed integrated circuits; integrated circuit technology; mixed analogue-digital integrated circuits; 0.12 micron; NMOS technology; RF analog circuit; cut-off frequency; high-speed digital circuit; mixed mode IC; noise figure; raised gate/source/drain; threshold voltage; undoped epitaxial channel; Annealing; CMOS logic circuits; CMOS technology; Electrodes; MOS devices; MOSFETs; Radio frequency; Temperature; Threshold voltage; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746506

Filename

746506